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d a t a sh eet product speci?cation file under integrated circuits, ic06 september 1993 integrated circuits 74hc/hct646 octal bus transceiver/register; 3-state for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
september 1993 2 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 features independent register for a and b buses multiplexed real-time and stored data output capability: bus driver i cc category: msi general description the 74hc/hct646 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct646 consist of bus transceiver circuits with 3-state outputs, d-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the internal registers. data on the a or b bus will be clocked into the registers as the appropriate clock (cp ab and cp ba ) goes to a high logic level. output enable ( oe) and direction (dir) inputs are provided to control the transceiver function. in the transceiver mode, data present at the high-impedance port may be stored in either the a or b register, or in both. the select source inputs (s ab and s ba ) can multiplex stored and real-time (transparent mode) data. the direction (dir) input determines which bus will receive data when oe is active (low). in the isolation mode ( oe = high), a data may be stored in the b register and/or b data may be stored in the a register. when an output function is disabled, the input function is still enabled and may be used to store and transmit data. only one of the two buses, a or b, may be driven at a time. the 646 is functionally identical to the 648, but has non-inverting data paths. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl / t plh propagation delay a n , b n to b n , a n c l = 15 pf; v cc =5v 11 13 ns f max maximum clock frequency 69 85 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per channel notes 1 and 2 30 33 pf
september 1993 3 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 pin description pin no. symbol name and function 1cp ab a to b clock input (low-to-high, edge-triggered) 2s ab select a to b source input 3 dir direction control input 4, 5, 6, 7, 8, 9, 10, 11 a 0 to a 7 a data inputs/outputs 12 gnd ground (0 v) 20, 19, 18, 17, 16, 15, 14, 13 b 0 to b 7 b data inputs/outputs 21 oe output enable input (active low) 22 s ba select b to a source input 23 cp ba b to a clock input (low-to-high, edge-triggered) 24 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
september 1993 4 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 fig.4 functional diagram. function table notes 1. h = high voltage level l = low voltage level x = dont care - = low-to-high level transition 2. the data output functions may be enabled or disabled by various signals at the oe and dir inputs. data input functions are always enabled, i.e., data at the bus inputs will be stored on every low-to-high transition on the clock inputs. inputs (1) data i/o (2) function oe dir cp ab cp ba s ab s ba a 0 to a 7 b 0 to b 7 h h x x h or l - h or l - x x x x input input isolation store a and b data l l l l x x x h or l x x l h output input real-time b data to a bus stored b data to a bus l l h h x h or l x x l h x x input output real-time a data to b bus stored a data to b bus
september 1993 5 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 fig.5 logic diagram.
september 1993 6 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay a n ,b n to b n ,a n 39 14 11 135 27 23 170 34 29 205 41 35 ns 2.0 4.5 6.0 fig.6 t phl / t plh propagation delay cp ab ,cp ba to b n ,a n 66 24 19 220 44 37 275 55 47 330 66 56 ns 2.0 4.5 6.0 fig.7 t phl / t plh propagation delay s ab ,s ba to b n ,a n 55 20 16 190 38 32 240 48 41 285 57 48 ns 2.0 4.5 6.0 fig.8 t pzh / t pzl 3-state output enable time oe to a n ,b n 47 17 14 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 fig.9 t phz / t plz 3-state output disable time oe to a n ,b n 58 21 17 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 fig.9 t pzh / t pzl 3-state output enable time dir to a n ,b n 50 18 14 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 fig.10 t phz / t plz 3-state output disable time dir to a n ,b n 50 18 14 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 fig.10 t thl / t tlh output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.6 and fig.8 t w clock pulse width high or low cp ab or cp ba 80 16 14 25 9 7 100 24 20 120 24 20 ns 2.0 4.5 6.0 fig.7 t su set-up time a n ,b n to cp ab ,cp ba 60 12 10 - 3 - 1 - 1 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.7 t h hold time a n ,b n to cp ab ,cp ba 35 7 6 6 2 2 45 9 8 55 11 9 ns 2.0 4.5 6.0 fig.7 f max maximum clock pulse frequency 6.0 30 35 21 63 75 4.8 24 28 4.0 20 24 mhz 2.0 4.5 6.0 fig.7
september 1993 7 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. input unit load coefficient s ab , s ba 0.60 a 0 to a 7 and b 0 to b 7 0.75 input unit load coefficient cp ab ,cp ba 1.50 oe dir 1.50 1.25
september 1993 8 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay a n ,b n to b n ,a n 16 30 38 45 ns 4.5 fig.6 t phl / t plh propagation delay cp ab ,cp ba to b n ,a n 23 44 55 66 ns 4.5 fig.7 t phl / t plh propagation delay s ab ,s ba to b n ,a n 26 46 58 69 ns 4.5 fig.8 t pzh / t pzl 3-state output enable time oe to a n ,b n 21 40 50 60 ns 4.5 fig.9 t phz / t plz 3-state output disable time oe to a n ,b n 20 35 44 53 ns 4.5 fig.9 t pzh / t pzl 3-state output enable time dir to a n ,b n 21 40 50 60 ns 4.5 fig.10 t phz / t plz 3-state output disable time dir to a n ,b n 21 35 44 53 ns 4.5 fig.10 t thl / t tlh output transition time 5 12 15 18 ns 4.5 fig.6 and fig.8 t w clock pulse width high or low cp ab or cp ba 16 8 20 24 ns 4.5 fig.7 t su set-up time a n ,b n to cp ab ,cp ba 12 3 15 18 ns 4.5 fig.7 t h hold time a n ,b n to cp ab ,cp ba 5 1 5 5 ns 4.5 fig.7 f max maximum clock pulse frequency 30 77 24 20 mhz 4.5 fig.7
september 1993 9 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 ac waveforms fig.6 waveforms showing the input a n , b n to output b n , a n propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.7 waveforms showing the a n ,b n to cp ab , cp ba set-up and hold times, clock cp ab ,cp ba pulse width, maximum clock pulse frequency and the cp ab ,cp ba to output b n ,a n propagation delays. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.8 waveforms showing the input s ab ,s ba to output b n ,a n propagation delays and output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v.
september 1993 10 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 fig.9 waveforms showing the input oe to output a n ,b n 3-state enable and disable times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.10 waveforms showing the input dir to output a n , b n 3-state enable and disable times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v.
september 1993 11 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 application information fig.11 data storage from a and/or b bus. fig.12 real-time transfer from bus a to bus b. fig.13 real-time transfer from bus b to bus a.
september 1993 12 philips semiconductors product speci?cation octal bus transceiver/register; 3-state 74hc/hct646 package outlines see 74hc/hct/hcu/hcmos logic package outlines .

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